LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY memparse IS 
	PORT(Newframe, clock, Newaddress		:	IN	STD_LOGIC;
		 srcadd, destadd		:	IN	STD_LOGIC_VECTOR(47 DOWNTO 0);
		 length	: 	IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 portno	:	IN STD_LOGIC_VECTOR(1 DOWNTO 0);
		 Addressin		: 	IN	STD_LOGIC_VECTOR(8 DOWNTO 0);
		 WriteAdd		:	OUT STD_LOGIC;
		 Addressout	:	OUT	STD_LOGIC_VECTOR(122 DOWNTO 0));
END memparse;

ARCHITECTURE Behavior OF memparse IS
	SIGNAL Q : STD_LOGIC_VECTOR(122 DOWNTO 0);
	SIGNAL Addressdone:	STD_LOGIC;
BEGIN
	PROCESS(clock)
	BEGIN
	IF Newframe ='1' THEN
		Q <= Q AND "0";
		Addressdone <= '0';
		WriteAdd <= '0';
	ELSIF(Clock'EVENT AND Clock = '1')THEN
		
		Q(24 DOWNTO 9) <= length;
		Q(72 DOWNTO 25) <= srcadd;
		Q(120 DOWNTO 73) <= destadd;
		Q(122 DOWNTO 121) <= portno;
		
		IF Newaddress = '1' THEN
			Q(8 DOWNTO 0) <= Addressin(8 DOWNTO 0);
			Addressdone <= '1';
		END IF;	
		
		IF Addressdone = '1' THEN
			WriteAdd <= '1';
			Addressout <= Q;
		END IF;
		
	END IF;	
	
	END PROCESS;
	

END Behavior;